Vertical integration (3D for short) processes and vertical interconnect techniques are being explored by industry for several applications, such as memories, pixel sensor arrays, microprocessors and FPGAs. They are deemed capable to make up for some important performance limitation facing CMOS feature size scaling. Digital circuits, in particular, may greatly benefit from interconnect length reduction both in terms of power dissipation and logical span of control. In the case of a heterogeneous integration approach, separate parts of the design can be manufactured using the process that best suits its specific needs, then assembled in a vertical stack. In general, the 3D approach enables the design of low mass, high density circuits with the possibility of isolating the various building blocks, for instance analog from digital parts. The workshop aims to bring together physicists and engineers working on the development of vertically integrated pixel sensors. Particular attention is paid to detector design for high energy physics (HEP) experiments at the future high luminosity colliders and for photon science applications. The main purpose of the workshop is to provide a place for the people working in the field to exchange ideas and share knowledge, and to make the community aware of the different options available to access vertical integration technologies.